1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
A memory cell array of a DRAM (Dynamic Random Access Memory) has a configuration in which memory cells, each including a transistor and a capacitor, are arranged in array-like manner, i.e. in row and column directions. In its operation, a word line selected by a row address rises to turn on the transistor connected to the word line. Each potential stored in the capacitor of a memory cell arranged in a certain row is thereby read out simultaneously by a sense amplifier via a bit line, and is amplified to the level xe2x80x9cHxe2x80x9d (array voltage, VDD) or xe2x80x9cLxe2x80x9d (VSS). The above-described bit line is pre-charged to a bit line pre-charge voltage, i.e. a constant voltage (VBL, generally VDD/2), until the above-described word line rises. A cell plate electrode is arranged as a common opposing electrode for a capacitor of each memory cell, and is fixed to a constant cell plate voltage (VCP, generally VDD/2).
In case of a DRAM having a large capacity, in order to accommodate with the increase of power consumption and access time, the memory cell array is divided into a large number of sub memory arrays and the word line is formed to have a hierarchical word configuration including a main word line and a sub word line.
FIG. 6 schematically shows a configuration of a multi-divided memory array and FIG. 7 is a detailed view of a sub memory array SMA, a sub word driver band SWD and a sense amplifier band SA.
Mainly referring to FIG. 6, in the multi-divided memory array, the memory cell array is divided into a large number of sub memory arrays SMA, and the sub word driver band SWD and the sense amplifier band SA are arranged for each of the plurality of sub memory arrays SMA. A main word line MWL extends in row direction crossing over the plurality of sub memory arrays SMA arranged in row direction, and a sub word line SWL connected to the main word line MWL via the sub word driver SWD also extends in row direction across each of the sub memory arrays SMA. The main word line MWL is driven by a main word driver MWD in response to the signals of a row decoder RD.
Mainly referring to FIG. 7, the sub memory array SMA has a plurality of memory cells MC arranged in a matrix. Each gate of the memory cells MC arranged in the same row is connected to the sub word line SWL, which is in turn connected to each of the drivers SWDa of the sub word driver band SWD. The memory cells MC arranged in the same column are respectively connected to one of a pair of bit lines BL and /BL. The bit-line pair BL and /BL is connected to any of the sense amplifiers S/A, illustrated at the top or the bottom in FIG. 7, via NMOS transistors NT 10 and NT 11 in which a shared gate signal SHRb is input to the respective gates.
In addition to a plurality of sense amplifiers S/A and a plurality of S/A shared circuits including NMOS transistors NT 10 to NT 13, the sense amplifier band SA has a plurality of equalizing circuits including NMOS transistors NT15 to NT17. These equalizing circuits are used to apply the pre-charge voltage VBL described above to the bit lines BL and /BL.
The sub word line SWL is driven by the sub word driver SWDa in response to the signals of the main word line MWL and a sub decoding line SDL.
The above-described memory cell MC has a one transistor-one capacitor configuration including a transistor 110 and a capacitor 120, as shown in FIG. 8, for example. As shown in FIG. 7, a cell plate 113 of capacitor 120 extends substantially over entire region of the sub memory array SMA. Cell plate 113 is connected, at several portions, to a VCP power-supply interconnection 117a extending in the vicinity of the border between the sub memory array SMA and the sub word driver band SWD, so that cell plate 113 is fixed to the cell plate voltage VCP.
An example of a conventional configuration for applying the cell plate voltage VCP to the cell plate is shown in FIG. 9.
Referring to FIG. 9, MOS transistors 110 and 130 are formed on the surface of a semiconductor substrate 101 electrically isolated by a trench isolation 102. MOS transistors 110 and 130 have pairs of source/drain regions 103 and 121 respectively, and the transistors have respective gate electrodes 105 and 123 formed on the regions sandwiched between the source/drain regions 103 and 121, with gate insulating layers 104 and 122 interposed, respectively. In particular, gate electrode 105 forms the sub word line SWL described above.
A bit line 107 and dummy bit lines 107a, 107b are formed on an interlayer insulating layer 106 covering MOS transistors 110 and 130. Bit line 107 is electrically connected to source/drain region 103 through a contact hole 106a. 
A COB (Capacitor Over Bitline) structure is employed in that a capacitor 120 is formed on an interlayer insulating film 108 covering bit line 107. Capacitor 120 is a stacked capacitor having a storage node 111 and a cell plate 113 opposing to storage node 111 with a capacitor dielectric layer 112 posed therebetween. Storage node 111 has a tubular portion extending upward and is electrically connected to source/drain region 103 through a contact hole 108a. 
A dummy storage node 111a is formed in a dummy region. A main word line 115 and an intermediate interconnection 115a are formed as the first metal interconnections on an interlayer insulating film 114 covering capacitor 120. Intermediate interconnection 115a is electrically connected to cell plate 113 through a contact hole 114a. 
A VCP power-supply interconnection 117a and an interconnection 117b are formed as the second metal interconnections on an interlayer insulating film 116 covering main word line 115 and intermediate interconnection 115a. VCP power-supply interconnection 117a is electrically connected to intermediate interconnection 115a via a through hole 116a. A power-supply interconnection, a GND interconnection and a global I/O interconnection are also formed as the second metal interconnections.
Thus, the feeding of the cell plate voltage VCP to the cell plate 113 has conventionally been provided from VCP power-source line 117a through intermediate interconnection 115a. 
As can be seen from FIG. 7, cell plate 113 having a large area approximately the same as the sub memory array is fed at several portions with the VCP power supply, whereby the potential is surely fixed. Insufficient fixation of the potential causes the variation of the potential of cell plate 113 upon continued writing of the same data in page mode operation, and the insufficient storage potential of the memory cell MC. xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d error tends to occur as the potential of cell plate 113 is raised, whereas xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d error tends to occur as the potential is lowered.
Although it has been described that VCP power-source line 117a is arranged on the border between the sub memory array region and the sub word driver band, it may also be arranged on the sub memory array region. In any case, by arranging VCP power-source line 117a in a region other than the sub word driver band, the increase in the width of the sub word driver band is prevented.
However, in the system LSI (Large Scale Integrated) circuit embedding DRAM, the method of feeding VCP to the above-described cell plate may not be used in some cases, as will be described in the following.
When the memory array is configured with the memory cells of the stacked-capacitor type, a large step is generated between the memory array portion and the other peripheral portion. Further, as shown in FIG. 9, the step in the interlayer insulating film 116 of an upper layer is larger than that in interlayer insulating film 114 of a lower layer. The height of the step of interlayer insulating film 116 could be 100 nm or more depending on the height of the stacked capacitor.
On the other hand, when forming a plurality of through holes or contact holes on a same process step, the through holes or the contact holes are required to have a uniform size (opening diameters) across the entire chip. This is because the etching characteristics upon forming the holes and the embedding characteristics upon embedding plugs into the through holes or the like are considered. It is thus impossible to partially enlarge the size of the through holes or the contact holes of a certain block.
Generally, in the system LSI, the size of the through holes or the contact holes is set small in order to increase the gate density of a logic block. It is thus necessary to accommodate the size of the through holes or the contact holes of the embedded DRAM portion to the smaller size of the logic block, since the size uniformity is required across the entire chip as described above. Thus, the size of the through holes or the contact holes on the memory array portion of the embedded DRAM will be smaller than those of a commodity DRAM where the memory cell array is configured with the memory cells of the same design dimension.
The size reduction then leads to the reduction of DOF (Depth of Focus) on a lithographic process, causing difficulties in the formation of the through holes or the contact holes in the memory array region and the stepped region described above. In particular, on the above-described interlayer insulating film 116 in which the step is larger, the through holes or the like cannot be placed, and should be placed in the region considerably inner side of the sub word driver band and/or the sense amplifier band.
For the reasons described above, VCP power-source line 117a needs to be arranged considerably inner side of the sub word driver band (right side in the drawing), and intermediate interconnection 115a needs to be extended from the region directly above cell plate 113 to the region directly below VCP power-source line 117a. 
Further, a local power-supply interconnection of VCP may possibly be arranged as the first metal interconnection. However, the main word line MWL is extending, from the memory array, orthogonally crossing the local power-supply interconnection of VCP at the first metal interconnection. The main word line MWL thus needs to be partly raised to the second metal interconnection so as to cross over the local power-supply interconnection of VCP. In this case also, the positions of the through holes are thereby restricted and the local power-supply interconnection needs to be arranged considerably inner side of the sub word driver band.
When the power-supply interconnection of VCP (VCP power-supply interconnection 117a or the local power-supply interconnection of VCP) is arranged in the sub word driver band SWD as described above, the width of the sub word driver band SWD is increased, because of the interconnection region of the power-supply interconnection of VCP, the connecting portion between the VCP power-supply interconnection and through hole 116a of intermediate interconnection 115a, and intermediate interconnection 115a running a significant distance transverse to the sub word driver band SWD. Thus, as the number of the division of sub memory array SMA in row direction is increased, the sum of the increased part of the width of the above-described sub word driver band SWD is increased, causing the problem in that the area of the chip is increased.
On the other hand, there is a method of feeding VCP in that the power-supply interconnection is arranged in parallel with the main word line MWL on the border between sub memory array SMA and sense-amplifier band SA, while connecting the power-supply interconnection to the cell plate at several portions. In this case, however, the width of sense amplifier band SA is increased by the interconnection region of the power-supply interconnection of VCP, causing the problem in that the area of the chip is increased as the number of the division of sub memory array SMA in column direction is increased.
An object of the present invention is to provide a semiconductor memory device, which ensures the feeding of a cell plate voltage to a cell plate, while preventing the increase of the chip area.
The semiconductor memory device of the invention includes a semiconductor substrate, a bit line, a dummy bit line, a capacitor and a first intermediate interconnection. The semiconductor substrate has a main surface. The bit line is formed on the main surface. The dummy bit line is formed from the same layer as and separately from the bit line. The capacitor has an upper electrode formed above the bit line. The first intermediate interconnection is formed above the capacitor and is electrically connected to the dummy bit line and an upper electrode.
In the semiconductor memory device of the present invention, the dummy bit line and the first intermediate interconnection are connected via a contact hole under the first intermediate interconnection. The influence of a step generated upon formation of the contact hole is thereby reduced compared to the conventional method in that a through hole is formed on the first intermediate interconnection. Thus, the contact hole for connecting the dummy bit line and the first intermediate interconnection can also be formed, for example, on the border between the sub memory array region and the sub word driver band. This eliminates the conventional need for forming the first intermediate interconnection and the contact hole connected thereto considerably inner side of the sub word driver band. Therefore, the increase of the width of the sub word driver and the area of the chip can be prevented.
Preferably, the semiconductor memory device described above further includes a pair of source/drain regions formed at the main surface, a sub word line extending on the region sandwiched between the pair of source/drain regions with the gate insulating layer interposed, and a main word line formed from the same layer as and separately from the first intermediate interconnection and forming a hierarchical word line configuration together with the sub word line.
The first intermediate interconnection can thus be formed from the same layer as and separately from the main word line and can efficiently be formed in the hierarchical word configuration.
In the semiconductor memory device described above, preferably, a plurality of memory cells are arranged, each including a transistor having a pair of source/drain regions and a gate electrode formed by the sub word line and a capacitor to configure a sub memory array. A memory cell array is configured by a plurality of sub memory arrays.
Thus, in a DRAM with a large capacity having a multi-divided memory array configuration, a predetermined potential can reliably be fed to the upper electrode of the capacitor, while preventing the increase of the area of the chip.
Preferably, the semiconductor memory device described above further includes an upper-layer interconnection formed above the first intermediate interconnection and electrically connected to the dummy bit line.
The predetermined potential to be applied to the upper electrode can thus be fed to the upper electrode from the upper-layer interconnection through a dummy bit line.
Preferably, the semiconductor memory device described above further includes a second intermediate interconnection formed from the same layer as and separately from the first intermediate interconnection. The upper-layer interconnection is electrically connected to the second intermediate interconnection with the dummy bit line interposed.
The second intermediate interconnection is thus provided between the dummy bit line and the upper-layer interconnection as described above, thereby facilitating the formation of the through hole for connecting the dummy bit line and the upper-layer interconnection.
In the semiconductor memory device described above, preferably, the voltage having a same level as the pre-charge voltage for the bit line is applied to the upper electrode via the dummy bit line and the first intermediate interconnection.
Thus, the same voltage as the pre-charge voltage can reliably be fed to the upper electrode.
Preferably, in the semiconductor memory device described above, the material of the first intermediate interconnection is made of metal, and the material of the bit line includes at least one of silicon and refractory metal.
The materials suitable for the first intermediate interconnection and the bit line are thus selected. The semiconductor memory device described above further includes an additional dummy bit line running in parallel with the dummy bit line. The dummy bit line and the additional dummy bit line are connected at several portions.
Therefore, even if the dummy bit line directly connected to the first intermediate interconnection is cut off, the first intermediate interconnection can still be fed by detouring the additional dummy bit line.
Preferably, in the semiconductor memory device described above, the first intermediate interconnection is disposed extending in parallel to the main word line.
Preferably, in the semiconductor memory device described above, the dummy bit line has a branch for connecting with the first intermediate interconnection.
Preferably, in the semiconductor memory device described above, the bit line is located at one side of the dummy bit line, and the branch extends to another side of the dummy bit line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.